Class AB amplifiers are well known devices and have many and varied uses. One such use is as a voltage source for switching circuits where a large amount of current is required during signal transition periods, but only a small current is required during steady state operation. Such amplifiers have found particular utility in providing a source voltage in CMOS integrated circuit designs.
One such class AB CMOS amplifier is described in the article entitled “Class AB CMOS Amplifiers With High Efficiency” by Callewaert et al., IEEE Journal of Solid-State Circuits, Vol. 25, No. 3, June 1990. This amplifier 51, which is reproduced in FIG. 1, has an output p-channel Q30 and n-channel Q27 transistors serially connected across voltage supply terminals 23, 25, with an output 21 being taken at the interconnection of the two transistors. The transistors Q27, Q30 are gate biased by respective differential amplifier stages 11, 15 and associated current sum branches 13, 17 through gate control signals developed at circuit nodes n2 and p4.
One exemplary use of the amplifier 51 is illustrated in FIG. 2 where amplifier 51 applies an output voltage to bias capacitors 43 and 45 of a sample-and-hold circuit 52 of a solid state CMOS imager device which reads output signals from pixels 31 arranged in an array of pixel rows and columns. The sample-and-hold circuit 52 is typically connected to a column line 35 to which is connected a plurality of pixel circuits 31 in parallel in respective rows of the pixel array. Column line 35 is coupled to a current source 41. Typically two output signals are provided by each pixel 31, a reset signal Vrst, and a signal Vsig representing incident light. These signals are respectively sampled through sample-and-hold switches 37 and 39 controlled by control signals SHR and SHS, respectively, to sample the reset signal Vrst on capacitor 43 and the light intensity signal Vsig on capacitor 45.
Prior to the sampling operation, clamping switches 47 and 49 are closed, and a clamping voltage provided by the class AB amplifier 51 is supplied to the back side of the capacitors. A clamp switch 48 is also typically provided for equalizing the voltages supplied to the capacitors 43, 45. After switches 47, 49, and 48 are closed to provide a voltage onto the back side of capacitors 43 and 45, the switches are then opened. The Vrst signal is sampled onto the capacitor 43 and the Vsig signal is sampled onto the capacitor 45. These signals are then respectively provided to positive and negative inputs of operational amplifier 53, and then to one or more amplifier stages 55, and finally to an analog-to-digital converter stage 57 where a differential analog signal Vrst−Vsig representing the amount of incident light on a pixel is digitized and used for image processing. It should be appreciated that there are many column lines in a CMOS imager, and that FIG. 2 represents the circuitry associated with one column line, or circuitry which can be multiplexed among a plurality of column lines to provide Vrst and Vsig signals for the various pixels in a pixel array.
As further shown in FIG. 2, class AB amplifier 51 has its output 21 fed back to a negative input, while the positive input receives a reference voltage Vref. This amplifier generally provides a very good output voltage during both transient periods and steady state operation. However, its operation is somewhat limited by the maximum possible gain which can be obtained, and the amplifier output is also sensitive to power supply noise. Power supply noise is a particular problem in digital imaging circuits, as the signal levels which are provided by pixels 31 are relatively low signal levels, so any noise in the output provided by class AB amplifier 51 to the back sides of capacitors 43 and 45 could affect the level of signal read by the sample-and-hold circuit 52 and provided ultimately to the analog-to-digital converter 57. Accordingly, an improved class AB amplifier having lower noise and improved gain is desired.